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www.fairchildsemi.com rev. 1.0.0 jul/15/05 features ? improved noise immunity ? improved load line accuracy ? ttl compatible vid inputs ? fully pin and function compatible with existing fan5019 and adp3188 controllers ? precision multi-phase dc-d c core voltage regulation ? 10mv output voltage a ccuracy over temperature ? differential remote voltage sensing ? selectable 2-, 3-, or 4-phase operation ? selectable vrm9 or vrm10 operation ? up to 1mhz per phase operation (4mhz ripple frequency) ? lossless inductor current sensing for loadline compensation ? external temperature compensation ? accurate loadline programming (meets intel ? vrm/vrd10.x cpu specifications) ? accurate channel-current balancing for thermal optimization and layout compensation ? convenient 12v supply biasing ? 6-bit voltage identification (vid) input ? .8375v to 1.600v in 12.5mv steps ? dynamic vid capability with fault-blanking for glitch-less output voltage changes ? adjustable over current protection with programmable latch-off delay. latch-off function may be disabled ? over-voltage protection ? internal ovp crowbar protection ? package: 28l-tssop applications ? vrm/vrd 9.x and 10.x computer dc/dc converter ? high-current, low-voltage dc/dc rail general description the fan5019b is a multi-phase dc-dc controller for implementing high-current, low-voltage, cpu core power regulation circuits. it is part of a chipset that includes exter- nal mosfet drivers and power mosfets. the fan5019b drives up to four synchronous-rectified buck channels in parallel. the mu lti-phase buck converter archi- tecture uses interleaved swit ching to multiply ripple fre- quency by the number of phases and reduce input and output ripple currents. lower ripple results in fewer components, lower component cost, reduced power dissipation, and smaller board area. the fan5019b features a high-bandwidth control loop to provide optimal response to load transients. the fan5019b senses current using lossless techniques: phase current is measured through each of the output inductors. this current information is summed, averaged and used to set the loadline of the output via programmable "droop." the droop is tem- perature compensated to achie ve precise loadline character- istics over the entire operating range. additionally, individual phase current is measured using the r ds(on) of the low-side mosfets. this information is used to dynam- ically balance/steer per-phase current. the phase currents are also summed and averaged for over-current detection. dynamic-vid technology allo ws on-the-fly vid changes with controlled, glitch-less output. additionally, short-circuit protection, adjustable current limiting, over-voltage protec- tion and power-good circuitry combine to ensure reliable and safe operation. fan5019b is specified over the commercial temperature range of 0c to +8 5c and operates from a sin- gle +12v supply which simplifies design. fan5019b is available in a 28l-tssop package. block diagram fan5019b v in v in 1 4 v ou t 3 2 fan5009 fan5009 fan5019b 6-bit vid controller 2-4 phase vr10.x controller
fan5019b product specification 2 rev. 1.0.0 jul/15/05 pin assignments pin definitions pin number pin name pin function description 1?5 vid [4:0] vid inputs. determines the output voltage via the internal dac. these inputs comply to vrm10/vrd10 specifications for static and dynamic operation. all have internal pull-ups (1.25v for vrm10 and 2.5v for vrm9) so leaving them open results in logic high. leaving vid[4:0] open results in a "no cpu" condition disabling the pwm outputs. 6 vid5/sel vid5 input/dac select. dual function pin that is either the 12.5mv dac lsb for vrm10 or selects the vrm9 dac codes when forced higher than vtblsel(vrm9) voltage. the truth table is as follows: v vid5/sel held > vtblsel(vrm9); vrm9 dac table is selected (see table 3) v vid5/sel < vtblsel(vrm10); vrm10 dac table is selected (see table 2) and v vid5/sel pin is used as vid5 input. 7fbrtn feedback return. error amp and dac reference point. 8fb feedback input. inverting input for error amp this pin is used for external compensation. this pin can also be used to introduce dc offset voltage to the output. 9comp error amp output. this pin is used for external compensation. 10 pwrgd power good output. this is an open-drain output that asserts when the output voltage is within the specified tolerance. it is expected to be pulled up to an external voltage rail. 11 en enable. logic signal that enables the controller when logic high. 12 delay soft-start and current limit delay. an external resistor and capacitor sets the softstart ramp rate and the over-current latch off delay. 13 rt switching frequency adjust. this pin adjusts the output pwm switching frequency via an external resistor. 14 rampadj pwm current ramp adjust. an external resistor to vcc will adjust the amplitude of the internal pwm ramp. 15 ilimit current limit adjust. an external resistor sets the current limit threshold for the regulator circuit. this pin is internally pulled low when en is low or the uvlo circuit is active. it is also used to enable the drivers. delay vid4 vid3 vid2 vid1 vid0 comp cscomp pwrgd en cssum rt vcc sw2 sw3 pwm3 pwm4 pwm1 gnd fbrtn ilimit fb csref rampadj 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 1 9 18 17 16 15 fan5019b tssop-28 sw1 pwm2 sw4 vid5/sel
product specification fan5019b rev. 1.0.0 jul/15/05 3 16 csref current sense reference. non-inverting input of the current sense amp. sense point for the output voltage used for ovp and pwrgd. 17 cssum current sense summing node. inverting input of the current sense amp. 18 cscomp current sense compensation node. output of the current sense amplifier. this pin is used, in conjunction with cssum to set the output droop compensation and current loop response. 19 gnd ground. signal ground for the device. 20?23 sw[4:1] phase current sense/balance inputs. phase-to-phase current sense and balancing inputs. unused phases should be left open. 24?27 pwm[4:1] pwm outputs. cmos outputs for driving external gate driver such as the fan5009. unused phases should be connected to ground. 28 vcc chip power. bias supply for the chip. connect directly to a +12v supply. bypass with a 1f mlcc capacitor. pin definitions (continued) pin number pin name pin function description
fan5019b product specification 4 rev. 1.0.0 jul/15/05 absolute maximum ratings absolute maximum ratings are the values beyond which the devi ce may be damaged or have its useful life impaired. func- tional operation under these conditions is not implied. thermal information recommended operat ing conditions (see figure 8) note: 1: ja is defined as 1 oz. copper pcb with 1 in 2 pad. parameter min. max. units supply voltage: vcc to gnd -0.3 +15 v voltage on fbrtn pin -0.3 +0.3 v voltage on sw1-sw4 (<250ns duration) -5 +25 v voltage on sw1-sw4 (>=250ns duration) -0.3 +15 v voltage on rampadj, cssum -0.3 vcc+0.3 v voltage on any other pin -0.3 +5.5 v parameter min. typ max. units operating junction temperature (t j )0+150c storage temperature ?65 +150 c lead soldering temperature, 10 seconds +300 c vapor phase, 60 seconds +215 c infrared, 15 seconds +220 c power dissipation (p d ) @ t a = 25c 2 w thermal resistance ( ja ) (see note 1) 50 c/w parameter conditions min. typ. max. units supply voltage vcc vcc to gnd 10.2 12 13.8 v ambient operating temperature 0 +85 c operating junction temperature (t j ) 0 +125
product specification fan5019b rev. 1.0.0 jul/15/05 5 electrical s pecifications (v cc = 12v, t a = 0c to +85c and fbrtn=gnd, using circ uit in figure 1, unless otherwise noted.) the ? denotes specifications which apply over the full operating temperature range. parameter symbol conditi ons min. typ. max. units error amplifier output voltage range v comp ? 0.5 3.5 v accuracy v fb relative to dac setting, referenced to fbrtn, cssum = cscomp, test circuit 3 vrm10 vrm9 ? ? -10 -12 +10 +12 mv line regulation v fb vcc=10v to 14v 0.05 % input bias current i fb ? -17 -15 -13 a fbrtn current i fbrtn ? 150 180 a output current i o(err) fb forced to v out ? 3% 300 500 a gain bandwidth product gbw comp = fb ( see note 2) 20 mhz dc gain c comp = 10pf ( see note 2) 77 db vid inputs input low voltage v il(vid) vrm10 vrm9 ? ? 0.4 0.8 v v input high voltage v ih(vid) vrm10 vrm9 ? ? 0.8 2.0 v v input current, vid low i il(vid) vid(x) = 0v ? -30 -20 a input current, vid high i ih(vid) vid(x) = 1.15v ? -2 2 a pull-up resistance r vid internal ? 35 60 115 k internal pull-up voltage vrm10 vrm9 ? ? 1.0 2.2 1.15 2.4 1.26 2.6 v v vid transition delay time 2 vid code change to fb change ? 400 ns ?no cpu? detection turn-off delay time 2 vid code change to 11111x to pwm going low ? 400 ns vid table select vtblsel to select vrm9 table to select vrm10 table (becomes vid5) ? ? 4 3.5 v v oscillator frequency f osc ? 200 4000 khz frequency variation f phase t a = +25c, r t = 250k , 4-phase t a = +25c, r t = 115k , 4-phase t a = +25c, r t = 75k , 4-phase ? 155 200 400 600 245 khz khz khz output voltage v rt r t = 100k to gnd ? 1.9 2.0 2.1 v rampadj pin accuracy v rampadj v rampadj = vdac = +2k ? (vin?vdac)/ (rr+2k) @ 20a ? -50 +50 mv rampadj input current i rampadj current into rampadj pin 0 100 a current sense amplifier offset voltage v os(csa) cssum?csref, test circuit 1 ? -1.5 +1.5 mv input bias current i bias(csa) ? -50 +50 na gain bandwidth product gbw comp = fb ( see note 2) 10 mhz notes: 1. all limits at operating temperature extremes are guaranteed by design, charac terization and statistical quality control 2. guaranteed by design ? not tested in production.
fan5019b product specification 6 rev. 1.0.0 jul/15/05 dc gain ( see note 2) 77 db input common mode range cssum and csref ? 03v positioning accuracy v fb comp = fb, test circuit 2 ? -84 -80 -76 mv output voltage range i cscomp = 100a ? 0.1 3.3 v output current i o(csa) fb forced to v out ? 3% source/sink 300 375 a current balance circuit input operating range v sw(x)cm ? -600 +200 mv input resistance r sw(x) sw(x) = 0v ? 20 30 40 k input current i sw(x) sw(x) = 0v ? -10 -7 -4 a input current matching i sw(x) sw(x) = 0v ? -5 +5 % current limit comparator ilimit output voltage normal mode in shutdown v ilimit(nm) v ilimit(sd) r ilimit = 250k i ilimit = -100a ? ? 2.9 3 3.1 400 v mv output curre nt, normal mode i ilimit(nm) r ilimit = 250k 12 a maximum output current v iilimit = 3v ? 60 a current limit threshold voltage v cl v csref ?v cscomp , r ilimit = 250k ? 105 125 150 mv current limit setting ratio v cl /i ilimit 10.4 mv/a latch-off delay threshold v delay in current limit ? 1.7 1.8 1.9 v latch-off delay time t delay r delay = 250k , c delay = 4.7nf 600 s soft start output current, soft start mode i delay(ss) during start-up, delay < 2.8v ? -25 -20 -15 a soft start delay time t delay(ss) r delay = 250k , c delay = 4.7nf, vid = 011111 (1.475v) 400 s enable input input low voltage v il(en) ? 0.4 v input high voltage v ih(en) ? 0.8 v input current, en low i il(en) en = 0v ? -1 1 a input current, en high i ih(en) en = 1.25v ? 10 25 a power good comparator under voltage threshold v pwrgd(uv) relative to dac output ? -325 -250 -200 mv over voltage threshold v pwrgd(ov) relative to dac output ? 90 150 200 mv output low voltage v ol(pwrgd) i pwrgd(sink) = 4ma ? 225 400 mv electrical s pecifications (continued) (v cc = 12v, t a = 0c to +85c and fbrtn=gnd, using circ uit in figure 1, unless otherwise noted.) the ? denotes specifications which apply over the full operating temperature range. parameter symbol conditi ons min. typ. max. units notes: 1. all limits at operating temperature extremes are guaranteed by design, charac terization and statistical quality control 2. guaranteed by design ? not tested in production.
product specification fan5019b rev. 1.0.0 jul/15/05 7 power good delay time initial start up vid code changing vid code static ? 1 100 250 200 10 ms s ns crowbar trip point v crowbar relative to nominal dac output ? 90 150 200 mv crowbar reset point relative to fbrtn ? 450 550 650 mv crowbar delay time vid code changing vid code static t crowbar over voltage to pwm going low ? 100 250 400 500 600 s ns pwm outputs output voltage low v ol(pwm) i pwm(sink) = 400a ? 160 500 mv output voltage high v oh(pwm) i pwm(source) = 400a ? 455.5v input supply dc supply current en = logic high ? 510ma uvlo threshold v uvlo vcc rising (vcc = 12v input) ? 6.5 6.9 7.8 v uvlo hysteresis ? 0.7 v uvlo threshold falling ? 5.6 7.0 electrical s pecifications (continued) (v cc = 12v, t a = 0c to +85c and fbrtn=gnd, using circ uit in figure 1, unless otherwise noted.) the ? denotes specifications which apply over the full operating temperature range. parameter symbol conditi ons min. typ. max. units notes: 1. all limits at operating temperature ex tremes are guaranteed by design, characte rization and statistical quality control 2. guaranteed by design ? not tested in production.
fan5019b product specification 8 rev. 1.0.0 jul/15/05 internal block diagram phase current balancing circuit vid dac ref current limit circuit oscillator uvlo shutdown & bias 11 28 1 9 13 14 cmp soft start 2/3/4 phase driver logic en reset set reset reset reset current limit crowbar 12 cmp cmp cmp csa error amp 24 25 26 27 20 21 22 23 + - 15 7 6 5 4 3 2 1 18 16 17 10 en 8 9 delay vid4 vid3 vid2 vid1 vid0 vid5 comp pwrgd en rt fbrtn fb rampadj cscomp cssum vcc sw2 sw3 pwm3 pwm4 pwm1 gnd ilimit csref sw1 pwm2 sw4 delay cmp cmp dac -250mv csref dac +150mv 2k 3.75v sel vrm 9 table
product specification fan5019b rev. 1.0.0 jul/15/05 9 typical characteristics test circuits tpc 1. master clock frequency tpc 2. supply current vs. master clock frequenc y 3.5 4 3 2.5 2 1.5 1 0.5 0 100 0 200 resistor?s rt value (k ) master clock frequency (mhz) 300 400 5.2 5.3 5.1 5.0 4. 9 4.8 4.7 4.6 1.0 0 2.0 master clock frequency (mhz) supply current (ma) 3.0 4.0 0.5 1.5 2.5 3.5 t a = 25 c 4-phase operation vcc 28 18 1 9 17 16 csref cssum cscomp gnd csa 100nf 3 9 k 1k 1v +12v 40 cscomp?1v v os = test circuit 1. current sense amplifier v os vcc 28 18 1 9 17 16 csref cssum cscomp gnd csa 100nf 200k 1v +12v 9 8 10k fb comp 200k 80mv vid fb v fb v ? = test circuit 2. voltage positioning vid4 vid0 vid1 vid2 vid3 vid5 fan5019b vcc 1 vid4 8 11 10 9 12 14 13 6 5 4 7 3 2 28 21 18 1 9 20 17 15 16 23 24 25 22 26 27 rampadj rt delay en pwrgd comp fb fbrtn vid5 vid0 vid1 vid2 vid3 ilimit csref cssum cscomp gnd sw4 sw3 sw2 sw1 pwm4 pwm3 pwm2 pwm1 250k 100nf 4.7nf 250k 20k 1 f 100nf +12v 1k test circuit 3. closed loo p out p ut volta g e accurac y
fan5019b product specification 10 rev. 1.0.0 jul/15/05 application circuit figure 1. typical application ? 3-phase, 65a (dc), 74a (peak) vrd/vrm10 design u1 fan500 9 4 6 2 3 8 1 5 7 hdrv vcc pgnd boot sw ldrv pwm od +12v u4 fan501 9 b vcc 1 vid4 8 11 10 9 12 14 13 6 5 4 7 3 2 28 21 18 1 9 20 17 15 16 23 24 25 22 26 27 rampadj rt delay en pwrgd comp fb fbrtn vid5/sel vid0 vid1 vid2 vid3 ilimit csref cssum cscomp gnd sw4 sw3 sw2 sw1 pwm4 pwm3 pwm2 pwm1 q4 l1 q5 q1 c x vcc core 0.8375v - 1.600v 74a dc, 9 3a peak c in +12v c dly r th * r t r dly c fb r a c a r b c b c cs r cs1 r sw1 r sw3 r sw2 r cs2 r ph1 r ph2 r ph3 c1 c4 c8 r1 9 c12 4 6 2 3 8 1 5 7 hdrv vcc pgnd boot sw ldrv pwm od q6 l2 q7 q2 +12v c2 c5 c 9 r20 c13 4 6 2 3 8 1 5 7 hdrv vcc pgnd boot sw ldrv pwm od q8 l3 q 9 q3 +12v c3 c6 c10 r21 c14 r lim c7 r r r1 r5 l4 v in v in v in pwrgd en c z r b1 u3 fan500 9 u2 fan500 9 note: the design shown in this datasheet should be used as a reference only. please contact your fairchild sales representative for t he latest information.
product specification fan5019b rev. 1.0.0 jul/15/05 11 bill of materials table 1. fan5019b vrm/vrd10 application bill of materials for figure 1 note: the design shown in this datasheet should be used as a refer ence only. please contact your fairchild sales representative for the latest information. ref qty description manufacturer/number u4 1 vr10, multi-phase cont roller fairchild fan5019b u1?3 3 sync mosfet driver, 12v/12v fairchild fan5009 q1?3 3 n-mosfet, 30v, 50a, 8m fairchild fdd6696 q4?9 6 n-mosfet, 30v, 75a, 5m fairchild fdd6682 l1?3 3 inductor, 650nh, 26a, 1.6m micrometals t50-8b/90, 5t, 16awg l4 1 inductor, 630nh, 15a, 1.7m inter-technical ak1418160052a-r63m r1 1 10 , 5% r r r dly , r t 3 301k , 1% r5 1 15.0k , 1% r ph1?3 3 100k , 1% r a , r cs2 2 24.9k , 1% r b1 1 10 , 1% r b 1 1.33k , 1% r sw1?3 3 0 , 5% r cs1 1 37.4k , 1% r lim 1 200k , 1% r19?21 3 1.5 , 5% r th 1 ntc thermistor, 100k , 5% panasonic ert-j1v v104j c1?7 7 1.0f, 25v, 10% x7r c8?10 3 0.1f, 50v, 10% x7r c12?14, c cs 4 4700pf, 25v, 10% x7r c dly 1 0.047f, 25v, 10% x7r c b 1 2200pf, 25v, 10% x7r c a 1 470pf, 50v, 10% x7r c fb 1 100pf, 50v, 5% npo c x 8 820f, 2.5v, 20% 7m , poly fujitsu fp-2r5re821m c z 22 10f, 6.3v, 20% x5r c in 6 470f, 16v, 20%, 36m , alum-elec rubycon 16mbz470m
fan5019b product specification 12 rev. 1.0.0 jul/15/05 table 2. vrm10 vid codes vid4 vid3 vid2 vid1 vid0 vid5 v out (nominal) 11111xno cpu 0 1 0 1 0 0 0.8375 v 0 1 0 0 1 1 0.8500 v 0 1 0 0 1 0 0.8625 v 0 1 0 0 0 1 0.8750 v 0 1 0 0 0 0 0.8875 v 0 0 1 1 1 1 0.9000 v 0 0 1 1 1 0 0.9125 v 0 0 1 1 0 1 0.9250 v 0 0 1 1 0 0 0.9375 v 0 0 1 0 1 1 0.9500 v 0 0 1 0 1 0 0.9625 v 0 0 1 0 0 1 0.9750 v 0 0 1 0 0 0 0.9875 v 0 0 0 1 1 1 1.0000 v 0 0 0 1 1 0 1.0125 v 0 0 0 1 0 1 1.0250 v 0 0 0 1 0 0 1.0375 v 0 0 0 0 1 1 1.0500 v 0 0 0 0 1 0 1.0625 v 0 0 0 0 0 1 1.0750 v 0 0 0 0 0 0 1.0875 v 1 1 1 1 0 1 1.1000 v 1 1 1 1 0 0 1.1125 v 1 1 1 0 1 1 1.1250 v 1 1 1 0 1 0 1.1375 v 1 1 1 0 0 1 1.1500 v 1 1 1 0 0 0 1.1625 v 1 1 0 1 1 1 1.1750 v 1 1 0 1 1 0 1.1875 v 1 1 0 1 0 1 1.2000 v 1 1 0 1 0 0 1.2125 v 1 1 0 0 1 1 1.2250 v 1 1 0 0 1 0 1.2375 v 1 1 0 0 0 1 1.2500 v 1 1 0 0 0 0 1.2625 v 1 0 1 1 1 1 1.2750 v 1 0 1 1 1 0 1.2875 v 1 0 1 1 0 1 1.3000 v 1 0 1 1 0 0 1.3125 v 1 0 1 0 1 1 1.3250 v
product specification fan5019b rev. 1.0.0 jul/15/05 13 1 0 1 0 1 0 1.3375 v 1 0 1 0 0 1 1.3500 v 1 0 1 0 0 0 1.3625 v 1 0 0 1 1 1 1.3750 v 1 0 0 1 1 0 1.3875 v 1 0 0 1 0 1 1.4000 v 1 0 0 1 0 0 1.4125 v 1 0 0 0 1 1 1.4250 v 1 0 0 0 1 0 1.4375 v 1 0 0 0 0 1 1.4500 v 1 0 0 0 0 0 1.4625 v 0 1 1 1 1 1 1.4750 v 0 1 1 1 1 0 1.4875 v 0 1 1 1 0 1 1.5000 v 0 1 1 1 0 0 1.5125 v 0 1 1 0 1 1 1.5250 v 0 1 1 0 1 0 1.5375 v 0 1 1 0 0 1 1.5500 v 0 1 1 0 0 0 1.5625 v 0 1 0 1 1 1 1.5750 v 0 1 0 1 1 0 1.5875 v 0 1 0 1 0 1 1.6000 v table 2. vrm10 vid codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 v out (nominal)
fan5019b product specification 14 rev. 1.0.0 jul/15/05 table 3. vrm9 vid codes vid4 vid3 vid2 vid1 vid0 v out (nominal) 11111no cpu 111101.100 v 111011.125 v 111001.150 v 110111.175 v 110101.200 v 110011.225 v 110001.250 v 101111.275 v 101101.300 v 101011.325 v 101001.350 v 100111.375 v 100101.400 v 100011.425 v 100001.450 v 011111.475 v 011101.500 v 011011.525 v 011001.550 v 010111.575 v 010101.600 v 010011.625v 010001.650v 001111.675v 001101.700v 001011.725v 001001.750v 000111.775v 000101.800v 000011.825v 000001.850v
product specification fan5019b rev. 1.0.0 jul/15/05 15 general description note: the information in this section is intended to assist users in their design and understanding of the fan5019b functionality. for clarity and ease of understanding, device parameters have been included in the text. in the event there are discrepancies between values stated in this section and the actual specification tables, the specification tables shall be deemed correct. theory of operation the fan5019b combines a multi-mode, fixed-frequency pwm control with multi-phase logic outputs for use in 2, 3 and 4 phase synchronous buck cpu core supply power con- verters. if vid5 is pulled up to a voltage greater than vtblsel, then the dac code corresponds to vrm9. multi-phase operation is important for producing the high currents and low voltages demanded by today?s micropro- cessors. handling the high currents in a single-phase con- verter would place high therma l demands on the components in the system, such as the inductors and mosfets. the internal 6-bit vid dac conforms to intel?s vrd/vrm 10 specifications. the multi-mode control of the fan5019b ensures a stable, high-performance topology for: ? balancing currents and thermals between phases ? high speed response at the lowest possible switching frequency and output decoupling ? minimizing thermal switching losses due to lower frequency operation ? tight load line regulation and accuracy ? high current output from having up to 4 phase operation ? reducing output ripple due to multi-phase cancellation ? pc board layout noise immunity ? ease of use and design due to independent component selection ? flexibility in operation for tailoring design to low cost or high performance number of phases the number of operational pha ses and their phase relation- ship is determined by internal circuitry which monitors the pwm outputs. normally, the fan5019b operates as a 4- phase pwm controller. grounding the pwm4 pin programs a 3-phase operation; grounding the pwm3 and pwm4 pins programs a 2-phase operation. when the fan5019b is initially enabled, the controller out- puts a voltage on pwm3 and pwm4 of approximately 550mv. an internal comparat or checks each pin?s voltage versus a threshold of 400mv. if the pin is grounded, then it will be below the threshold and the phase will be disabled. the output impedance of the pwm pin is approximately 5k . any external pull-down re sistance connected to the pwm pin should not be less than 25k to ensure proper operation. the phase detection is made prior to starting nor- mal operation. after this time, if the pwm output was not grounded, then it will operate normally. if the pwm output was grounded, then it will remain off. the pwm outputs become logic-level output devices once normal operation starts, and are intended for driving external gate drivers. since each phase is monitored independently, operation approaching 100% duty cycle is possible. also, more than one output can be on at a time for overlapping phases. master clock frequency the clock frequency of the fan5019b is set with an exter- nal resistor connected from the rt pin to ground. the fre- quency follows the graph shown in tpc 1. to determine the frequency per phase, the clock is divided by the number of phases in use. if pwm4 is grounded, then divide the master clock by 3 and if both pwm3 and 4 are grounded, then divide by 2. if all phases are in use, divide by 4. output voltage differential sensing the fan5019b provides a high accuracy vid dac and error-amplifier to maintain a 10 mv output setpoint toler- ance over temperature. output voltage is differentially sensed between the fb and fbrtn pins. fb should be con- nected through a resistor to the regulation point, usually the remote sense pin of the microprocessor. fbrtn should be connected directly to the remo te sense ground point. the internal vid dac an d precision reference are referenced to fbrtn, which has a typical current of 150a, to allow accurate remote sensing. the internal error amplifier com- pares the output of the dac to the fb pin to regulate the out- put voltage. output current sensing the fan5019b provides a dedi cated current sense amplifier (csa) to monitor the total output current for proper voltage positioning versus load current and for current limit detec- tion. sensing the load current at the output gives the total average current being delivere d to the load, which is an inherently more accurate method than peak current detection or sampling the current across a sense element such as the low side mosfet. there are several ways of configuring this amplifier depending on the objectives of the system: ? output inductor dcr sensing without thermistor for lowest cost ? output inductor dcr sensing with thermistor for improved accuracy with tracki ng of inductor temperature ? sense resistors for highest accuracy measurements the positive input of the csa is connected to the csref pin, which is connected to the output voltage. the inputs to the amplifier are summed together through resistors from the sensing element (such as the switch node side of the output inductors) to the inverting input, cssum. the feedback resistor between cscomp and cssum sets the gain of the
fan5019b product specification 16 rev. 1.0.0 jul/15/05 amplifier, and a filter capacitor is placed in parallel with this resistor. the amplifier?s gain is programmable by adjusting the feedback resistor to set the load line required by the microprocessor. the current info rmation is then given as the difference of csref ?cscomp. this difference signal is used internally to offset the vid dac for voltage position- ing and as a differential input for the current limit compara- tor. to provide the best accuracy for the current sensing, the csa is designed to have a low offset input voltage. also, external resistors determine the sensing gain so that it can be made extremely accurate and flexible. active impedance control mode for controlling the output voltage droop as a function of output current, the current sense amplifier (csa) creates a voltage signal proportional to the total inductor currents. external components determine the ratio of this voltage to the output current to allow it to be adjusted to set the required load line. inside the chip the csa output voltage is subtracted from the dac voltage which then is used for the reference to the error amplif ier. as the output current increases the reference to th e error amp decreases causing the output voltage to decrease accordingly. current control mode and thermal balance the fan5019b has individual inputs for each phase which are used for monitoring the curr ent in each phase. this infor- mation is combined with an inte rnal ramp to create a current balancing feedback system that is optimized for initial cur- rent balance accuracy and dynamic thermal balancing during operation. this current balance information is independent of the average output current information used for position- ing described previously. the magnitude of the internal ramp can be set to optimize the transient response of the syst em. it also monitors the sup- ply voltage for feed-forward co ntrol for changes in the sup- ply. a resistor connected from the power input voltage to the rampadj pin determines the slope of the internal pwm ramp. detailed information about programming the ramp is given in the application information section. external resistors can be placed in series with individual phases to create an intentional current imbalance if desired, such as when one phase may have better cooling and can support higher currents. resistors r sw1 through r sw4 (see the typical application circu it in figure 4) can be used for adjusting fet thermal and current balance. zero ohm placeholder resistors should be pr ovided in the initial layout to allow the phase balance to be adjusted during design fine tuning. to increase the current in any given phase, make r sw for that phase larger (make r sw = 0 for the hottest phase and do not change during balancing). increasing r sw to only 500 will substantially in crease the phase current. increase each r sw value by small amounts to achieve balance, starting with the co olest phase first. voltage control mode the voltage-mode control loop uses a high gain-bandwidth voltage mode error amplifier. the control input voltage to the positive input is set via th e vid 6-bit logic code, accord- ing to the voltages listed in table 1. this voltage is also off- set by the droop voltage for active positioning of the output voltage as a function of current, commonly known as active voltage positioning. the output of the amplifier is the comp pin, which sets the termination voltage for the internal pwm ramps. the negative input (f b ) is tied to the output sense location with a resistor r b and is used for sensing and controlling the output voltage at this point. a current source from the f b pin flowing through r b is used for setting the no-load offset voltage from the vid voltage. the no-load voltage will be negative with respect to the vid dac. the main loop com- pensation is incorporated in the feedback network between fb and comp. soft-start the power-on ramp up time of th e output voltage is set with a capacitor and resistor in pa rallel from the delay pin to ground. the rc time constant al so determines the current limit latch off time as explained in the following section. in uvlo or when en is a logic low, the delay pin is held at ground. after the uvlo threshold is reached and en is a logic high, the delay cap is charged up with an internal 20a current source. the output voltage follows the ramp- ing voltage on the delay pin, limiting the inrush current. the soft-start time depends on the value of vid dac and c dly , with a secondary effect from r dly . refer to the appli- cation information section for detailed information on set- ting c dly . if en is taken low or vcc drops below uvlo, the delay cap is reset to ground to be ready for another soft start cycle. figure 1 shows a typical start-up sequence for the fan5019b. over current limit and latch-off protection the fan5019b compares a pr ogrammable current limit set point to the voltage from the output of the current sense amplifier. the level of current limit is set with the resistor from the ilimit pin to groun d. during normal operation, the voltage on ilimit is 3v. the current through the exter- nal resistor is internally scaled to give a current limit thresh- old of approximately 10.4mv/a. if the difference in voltage between csref and cscomp rises above the cur- rent limit threshold, the internal current limit amplifier will control the internal comp voltage to maintain the average output current at the limit.
product specification fan5019b rev. 1.0.0 jul/15/05 17 after the limit is reached, the 3v pull-up on the delay pin is disconnected, and the exte rnal delay capacitor is dis- charged through the external re sistor. a comparator monitors the delay voltage and shuts of f the controller when the voltage drops below 1.8v. therefore, the rc time constant discharging from 3v to 1.8v sets the current limit latch off delay time. the application information section discusses the selection of c dly and r dly . because the controller continues to cycle the phases during the latch-off delay time, if the short is removed before the 1.8v threshold is r eached, the controller will return to nor- mal operation. the recovery ch aracteristic depends on the state of pwrgd. if the output voltage is within the pwrgd window, the controller resumes normal operation. however, if a short circuit has caused the output voltage to drop below the pwrgd threshold, then a soft-start cycle is initiated. the latch-off function can be rese t by either cycling vcc to the fan5019b, or by cycling the enable pin low for a short time. to disable the short circuit latch off function, the external resistor to ground should be left open, and a 1m resistor should be connected from vcc to the delay pin. this prevents the delay capacitor from discharging, so the 1.8v threshold is never reached . the resistor will have an impact on the soft-start time because the current through it will add to the internal 20a current source. during start-up when the output voltage is below 200mv, a secondary current limit is active. this is necessary because the voltage swing of cscomp cannot go below ground. this secondary current limit controls the internal comp voltage to the pwm comparators to 2v. this will limit the voltage drop across the low-side mosfets through the current balance circuitry. there is also an inherent per phase current limit that will pro- tect individual phases if one or more phases stops function- ing because of a faulty component. this limit is based on the maximum normal-mode comp voltage. dynamic vid the fan5019b incorporates the ability to dynamically change the vid input while the controller is running. this allows the output voltage to change while the supply is run- ning and supplying current to the load. this is commonly referred to as vid-on-the-fly (otf). a vid-otf can occur under either light load or heavy load conditions. the proces- sor signals the controller by changing the vid inputs in mul- tiple steps from the start code to the finish code. this change can be either positive or negative. when a vid input changes stat e, the fan5019b detects the change and ignores the dac inputs for a minimum of 400ns. this time is to prevent a fals e code due to logic skew while the six vid inputs are changing. additionally, the first vid change initiates the pwrgd and crowbar blanking functions for a minimum of 250s to prevent a false pwrgd or crowbar event. e ach vid change will reset the internal timer. figure 4 shows the vid on-the-fly perfor- mance when the output voltage is stepping up and the output current is switching between minimum and maximum values which is the worst-case situation. figure 4. vid on-the-fly waveforms, circuit of figure 5, vid change = 5mv, 5s, 50 steps, i out change = 5a to 65a figure 2. start-up wavef orms figure 3. overcure nt latch off waveform circuit of figure 5circuit of figure 5 channel 1 ? vout, channel 2 ? vccchannel 1 ? vcc, channel 2 ? vout channel 3 ? od, channel 4 ? delay pinchannel 3 ? od, channel 4 ? delay pin
fan5019b product specification 18 rev. 1.0.0 jul/15/05 power good monitoring the power good comparator monitors the output voltage via the csref pin. the pwrgd pin is an open drain output whose high level (when connected to a pull-up resistor) indi- cates that the output voltage is within the nominal limits specified in the specifications table based on the vid voltage setting. pwrgd will go low if the output voltage is outside of this specified range. pwrgd is blanked during a vid otf event for a period of 250 s to prevent false signals dur- ing the time the output is changing. output crowbar as part of the protection for the load and output components of the supply, the pwm outputs will be driven low (turning on the low-side mosfets) wh en the output voltage exceeds the upper power good threshold. this crowbar action will stop once the output voltage has fallen below the release threshold of approximately 550mv. turning on the low-side mosfets pulls down the output voltage as the reverse current builds up in the inductors. if the output overvoltage is due to a short of the high-side mosfet, this action will current limit the input supply or blow its fuse, protecti ng the microprocessor from destruction. output enable and uvlo the input supply (vcc) to the controller must be higher than the uvlo threshold and the en pin must be higher then its logic threshold for the fan5019b to begin switching. if uvlo is less than the threshold or the en pin is a logic low, the fan5019b is disabled. this holds the pwm outputs at ground, shorts the delay cap acitor to ground, and holds the ilimit pin at ground. in the application circuit, the ilimit pin should be con- nected to the output disable pins of the fan5009 drivers. because ilimit is grounded, th is disables the drivers such that both drvh and drvl ar e grounded. this feature is important to prevent discharging of the output capacitors when the controller is shut off. if the driver outputs were not disabled, then a negative voltage could be generated on the output due to the high current discharge of the output capacitors through the inductors. application information the design parameters for a typical intel vrd10.x-compli- ant cpu application are as follows: ? input voltage (v in ) = 12v ? vid setting voltage (v vid ) = 1.500v ? duty cycle (d) = 0.125 ? nominal output voltage at no load (v onl ) = 1.480v ? nominal output voltage at 65a load (v ofl ) = 1.3955v ? static output voltage drop based on a 1.3 m load line (r o ) from no load to full load ?(v d ) = v onl ? v ofl = 1.480v ? 1.3955v = 84.5mv ? maximum output current (i o ) = 65a ? maximum output current step ( i o ) = 60a ? number of phases (n) = 3 ? switching frequency per phase (f sw ) = 228 khz setting the clock frequency the fan5019b uses a fixed-frequency control architecture with the frequency being set by an external timing resistor (r t ). the clock frequency and the number of phases deter- mine the switching frequency per phase, which relates directly to switching losses a nd the sizes of the inductors and input and output capacitors. with n = 3 for three phases, a clock frequency of 684khz sets the switching frequency of each phase, f sw , to 228khz, which represents a practical trade-off between the switchin g losses and the sizes of the output filter components. tp c 1 shows that to achieve a 684khz oscillator frequency, the correct value for r t is 301k . alternatively, the value for r t can be calculated using: where 5.0pf and 110ns are internal ic component values. for good initial accuracy and fr equency stability, it is recom- mended to use a 1% resistor. soft-start and current limit latch-off delay times because the soft-start and current limit latch off delay functions share the delay pin, these two parameters must be considered together. the first step is to set c dly for the soft-start ramp. this ramp is generated with a 20a internal current source. the value of r dly will have a second order impact on the soft-start time b ecause it sinks part of the cur- rent source to ground. however, as long as r dly is kept greater than 200k , this effect is minor. the value for c dly can be approximated using: ( ) ns pf f n r sw t 110 5 1 ? = (1)
product specification fan5019b rev. 1.0.0 jul/15/05 19 where t ss is the desired soft-start time. assuming an r dly of 301k and a desired a soft-start time of 3ms, c dly is 35nf. a close standard value for c dly is 47nf. once c dly has been chosen, r dly can be calculated for the current limit latch-off time using: if the result for r dly is less than 200k , then a smaller soft- start time should be consider ed by recalculating the equation for c dly or a longer latch-off time should be used. r dly should never be less than 200k . in this example, a delay time of 8ms gives r dly = 334k . a close standard 1% value is 301k . inductor selection the choice of inductance value for the inductor determines the ripple current in the induc tor. less inductance leads to more ripple current, which incr eases the output ripple volt- age and conduction losses in the mosfets, but allows the use of smaller-size inductors and, for a specified peak-to- peak transient deviation, less total output capacitance. con- versely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger inductors and more output capacitance for the same peak-to-peak transient deviation. in any multi-phase converter, a practical value for the peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. equation 4 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ri pple current in the inductor. equation 5 can be used to determine the minimum induc- tance based on a given output ripple voltage: solving equation 5 for a 10 mv p-p output ripple voltage yields: if the ripple voltage ends up less than that designed for, the inductor can be made smaller until the ripple value is met. this will allow optimal transient response and minimum output decoupling. the smallest possible inductor should be used to minimize the number of output capacitors. choosing a 650nh inductor is a good choice for a starting point and gives a calculated ripple current of 8.86a. the inductor should not saturate at the peak current of 26.1a and should be able to handle the sum of the power dissipation cau sed by the average current of 21.7a in the winding and core loss. another important factor in the inductor design is the dc resistance (dcr), which is us ed for measuring the phase currents. a large dcr will cau se excessive power losses, while too small a value will l ead to increased measurement error. a good rule of thumb is to have the dcr be about 1 to 1 1/2 times the droop resistance (r o ). for our example, we are using an inductor with a dcr of 1.6 m . designing an inductor once the inductance and direct-current resistance (dcr) are known, the next step is ei ther to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. it is also important to have the inductance and dcr tolera nce specified to keep the accuracy of the system contro lled. using 15% for the induc- tance and 8% for the dcr (at room temperature) are reason- able tolerances that mo st manufacturers can meet. the first decision in designing the inductor is to choose the core material. there are several possibilities for providing low core loss at high freque ncies. two examples are the powder cores (e.g., kool-mm ? from magnetics, inc. or micrometals) and the gapped so ft ferrite cores (e.g., 3f3 or 3f4 from philips). low-frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. the best choice for a core ge ometry is a closed-loop type, such as pot cores, pq, u, an d e cores, or toroids. a good compromise between price and performance are cores with a toroidal shape. there are many useful referen ces for quickly designing a power inductor, such as: magnetics design references 1. magnetic designer software: intusoft (www.intusoft.com) 2. designing magnetic components for high-frequency dc-dc converters, by william t. mclyman, kg magnetics, inc. isbn 1883107008 vid ss dly vid dly v t r v a c ? ? ? ? ? ? ? = 2 20 (2) dly delay dly c t r = 96 . 1 (3) () l f d v i sw o r ? = 1 (4) () () ripple sw o vid v f d n r v l ? 1 (5) () nh mv khz m v l 534 10 228 375 . 0 1 3 . 1 5 . 1 = ?
fan5019b product specification 20 rev. 1.0.0 jul/15/05 selecting a standard inductor the companies listed below can provide design consultation and deliver power inductors optimized for high power applications upon request. power inductor manufacturers ?coilcraft (847)639-6400 www.coilcraft.com ? coiltronics (561)752-5000 www.coiltronics.com ? sumida electric company (510) 668-0660 www.sumida.com ? vishay intertechnology (402) 563-6866 www.vishay.com output droop resistance the design requires that the regulator output voltage measured at the cpu pins dr ops when the output current increases. the specified voltage drop corresponds to a dc output resistance (r o ). the output current is measur ed by summing together the voltage across each inductor and then passing the signal through a low-pass filter. this summer-filter is the cs amplifier configured with resistors r ph(x) (summers), and r cs and c cs (filter). the output resistance of the regulator is set by the following equations, where r l is the dcr of the output inductors: one has the flexibility of choosing either r cs or r ph(x) . it is best to select r cs equal to 100k , and then solve for r ph(x) by rearranging equation 6. next, use equation 7 to solve for c cs : it is best to have a dual location for c cs in the layout so stan- dard values can be used in parallel to get as close to the value desired. for this example, choosing c cs to be 4.7nf is a good choice. for best accuracy, c cs should be a 5% or 10% npo capacitor. a close standard 1% value for r ph(x) is 100k . inductor dcr temperature correction with the inductor?s dcr being used as the sense element, and copper wire being the source of the dcr, one needs to compensate for temperature ch anges of the inductor?s wind- ing. fortunately, copper has a well-known temperature coef- ficient (tc) of 0.39%/c. if r cs is designed to have an opposite and equal percentage change in resistance to that of the wire, it will cancel the temperature variation of the inductor?s dcr. due to the non- linear nature of ntc thermistors, resistors r cs1 and r cs2 are needed (see figure 5) to linearize the ntc and produce the desired temper ature tracking. figure 5. temperature compensation circuit the following procedure and expressions will yield values to use for r cs1 , r cs2 , and r th (the thermistor value at 25c) for a given r cs value. 1. select an ntc to be used based on type and value. since we do not have a value yet, start with a thermistor with a value close to r cs . the ntc should also have an initial tolerance of better than 5%. 2. based on the type of ntc, find its relative resistance value at two temperatures. th e temperatures to use that work well are 50c and 90c. we will call these resis- tance values a (r th(50c) )/r th(25c) ) and b (r th(90c) / r th(25c) ). note that the ntc?s relative value is always 1 at 25c. 3. next, find the relative value of r cs required for each of these temperatures. this is based on the percentage change needed, which we will initially make 0.39%/c. we will call these r 1 and r 2 where: l x ph cs o r r r r = ) ( (6) cs l cs r r l c = (7) cs o l x ph r r r r = ) ( = = k k m m r x ph 123 100 3 . 1 6 . 1 ) ( nf k m nh c cs 06 . 4 100 6 . 1 650 = = 18 17 16 csref cssum cscomp csa c cs 1.8nf r cs1 r cs2 r th r ph1 r ph3 r ph2 keep this path as short as possible and well away from switch node lines place as close as possible to nearest inductor or low-side mosfet to switch nodes to v out sense () ( ) 25 1 1 1 1 ? + = t tc r () ( ) 25 1 1 2 2 ? + = t tc r tc = 0.0039 t 1 = 50? t 2 = 90?
product specification fan5019b rev. 1.0.0 jul/15/05 21 4. compute the relative values for r cs1 , r cs2 , and r th using: 5. calculate r th = r th x r cs , then select the closest value of thermistor availa ble. also compute a scaling factor k based on the ratio of the actual thermistor value used relative to the computed one: 6. finally, calculate values for r cs1 and r cs2 using the following: for this example, r cs has been chosen to be 100k , so we start with a thermistor value of 100k . looking through available 0603 size thermist ors, we find a panasonic ert-j1vv104j ntc thermistor with a = 0.2954 and b = 0.05684. from these we compute r cs1 = 0.3304, r cs2 = 0.7426 and r th = 1.165. solving for r th yields 116.5 k , so we choose 100k , making k = 0.8585. finally, we find r cs1 and r cs2 to be 28.4k and 77.9k . choosing the closest 1% resistor valu es yields a choice of 35.7k and 73.2k . output offset intel?s specification re quires that at no load the nominal out- put voltage of the regulator be offset to a lower value than the nominal voltage corresponding to the vid code. the off- set is set by a constant curren t source flowing out of the fb pin (ifb) and flowing through rb. the value of rb can be found using equation 11: the closest standard 1% resistor value is 1.33 k . c out selection the required output decoupling for the regulator is typically recommended by intel for various processors and platforms. there are also some simple de sign guidelines to determine what is required. these guidelines are based on having both bulk and ceramic capacitors in the system. the first step is to select th e total amount of ceramic capaci- tance. this is based on the number and type of capacitor to be used. the best location for ceramics is inside the socket, with 12 to 18 of size 1206 being the physical limit. others can be placed along the outer edge of the socket as well. combined ceramic values of 200f?300f are recom- mended, usually made up of multiple 10f or 22f capacitors. select the number of ceramics and find the total ceramic capacitance (c z ). next, there is an upper limit imposed on the total amount of bulk capacitance (c x ) when one considers the vid on-the- fly voltage stepping of the output (voltage step v v in time t v with error v err ) and a lower limit based on meeting the crit- ical capacitance for load rel ease for a given maximum load step i o : to meet the conditions of these expressions and transient response, the esr of the bulk capacitor bank (r x ) should be less than two times the droop resistance, r o . if the c x(min) is larger than c x(max) , the system will not meet the vid on-the-fly specification and may require the use of a smaller inductor or more phases (and may have to increase the switching frequency to keep the output ripple the same). for our example, 22 10 f 1206 mlc capacitors (c z = 220f) were used. the vid on-the-fly step change is 250mv in 150s with a setting error of 2.5mv. solving for the bulk capacitance yields: ) ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) ( 2 1 1 2 2 1 2 b a r a b r b a r a b r b a r r b a r cs ? ? ? ? ? ? + ? ? ? = 2 1 2 1 1 1 ) 1 ( cs cs cs r r a r a r ? ? ? ? = (8) 1 2 1 1 1 1 cs cs th r r r ? ? = ) ( ) ( calculated th actual th r r k = (9) 1 1 cs cs cs r k r r = (10) ()( ) () 2 2 1 cs cs cs r k k r r + ? = fb onl vid b i v v r ? = (11) = ? = k a v v r b 33 . 1 15 480 . 1 5 . 1 ? ? ? ? ? ? ? ? ? z vid o o min x c v r n i l c ) ( (12) z o v vid v vid v o max x c l nkr v v t v v r nk l c ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 1 1 2 2 2 ) ( (13) where ? ? ? ? ? ? ? ? ? = v verr v v k ln
fan5019b product specification 22 rev. 1.0.0 jul/15/05 mf f v m a nh c min x 45 . 6 220 5 . 1 3 . 1 3 60 650 ) ( = ? ? ? ? ? ? ? ? ( ) m f f nh mv m v s v m mv nh c max x 9 . 23 220 1 650 250 3 . 1 6 . 4 3 5 . 1 150 1 5 . 1 3 . 1 6 . 4 3 250 650 2 2 2 ) ( = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? where k=4.6 using eight 820f a1-polys with a typical esr of 8m , each yields cx = 6.56 f with an rx = 1.0m . one last check should be made to ensu re that the esl of the bulk capacitors (lx) is low enough to limit the initial high- frequency transient spike. this can be tested using: in this example, l x is 375ph for the eight a1-poly capaci- tors, which satisfies this limitation. if the l x of the chosen bulk capacitor bank is too large, the number of mlc capaci- tors must be increased. note: for this multi-mode control technique, ?all- ceramic? designs can be used as long as the conditions of equations 11, 12 and 13 are satisfied. power mosfets for this example, the n-chan nel power mosfets have been selected for one high-side switch and two low-side switches per phase. the main selection parameters for the power mosfets are v gs(th) , q g , c iss , c rss and r ds(on) . the minimum gate drive voltage (the supply voltage to the fan5009) dictates whether standard threshold or logic-level threshold mosfets must be used. with v gate ~10v, logic-level threshold mosfets (v gs(th) < 2.5v) are recommended. the maximum output current i o determines the r ds(on) requirement for the low-side (synchronous) mosfets. with the fan5019b, currents are balanced between phases, thus the curr ent in each low-side mosfet is the output current divided by the total number of mosfets (n sf ). with conduction losses being dominant, the following expression shows the total power being dissipated in each synchronous mosfet in terms of the ripple current per phase (i r ) and average total output current (i o ): knowing the maximum output current being designed for and the maximum allowed power dissipation, one can find the required r ds(on) for the mosfet. for d-pak mosfets up to an ambient temp erature of 50oc, a safe limit for p sf is 1w?1.5w at 125oc junction temperature. thus, for our example (65a maximum), we find r ds(sf) (per mosfet) < 8.7m . this r ds(sf) is also at a junction temperature of about 125oc, so we need to make sure we account for this when making this selection. for our exam- ple, we selected two lo wer side mosfets at 8.6m each at room temperature, which gives 8.4m at high temperature. another important factor for the synchronous mosfet is the input capacitance and feedback capacitance. the ratio of the feedback to input needs to be small (less than 10% is recommended), to prevent accide ntal turn-on of the synchro- nous mosfets when the switch node goes high. also, the time to switch the synchronous mosfets off should not exceed the non-ove rlap dead time of the mosfet driver (40ns typical for the fan5009). the output impedance of the driver is about 2 and the typical mosfet input gate resistances are about 1 ?2 , so a total gate capacitance should be less than 6000pf. since there are two mosfets in parallel, we should limit the input capaci- tance for each synchronous mosfet to 3000pf. the high-side (main) mosfet has to be able to handle two main power dissipation components; conduction and switch- ing losses. the switching loss is related to the amount of time it takes for the main mosfet to turn on and off, and to the current and voltage that are being switched. basing the switching speed on the rise and fall time of the gate driver impedance and mosfet input capacitance, the following expression provides an approxim ate value for the switching loss per main mosfet, where n mf is the total number of main mosfets: here, r g is the total gate resistance (2 for the fan5009 and about 1 for typical high speed switching mosfets, making r g = 3 ) and ciss is the input capacitance of the main mosfet. adding more main mosfets (nmf) does not significantly help the switching loss per mosfet since the additional gate capacitance slows down switching. the best way to reduce switching lo ss is to use lower gate capac- itance devices. the conduction loss of the main mosfet is given by the following, where r ds(mf) is the on-resistance of the mosfet: 2 o r c l z x (14) () ph m f l x 372 3 . 1 220 2 = ? ( ) ) ( 2 2 12 1 1 sf ds sf r sf o sf r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? = (15) iss mf g mf o cc sw mf s c n n r n i v f p = 2 ) ( (16) ) ( 2 2 ) ( 12 1 mf ds mf r mf o mf c r n i n n i d p ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = (17)
product specification fan5019b rev. 1.0.0 jul/15/05 23 typically, for main mosfets, one wants the highest speed (low c iss ) device, but these usually have higher on-resistance. select a device that meets the total power dissipation (about 1.5 w for a single d-pak) when combin- ing the switching and conduction losses. for our example, we have sel ected a fairchild fd6696 as the main mosfet (three total; n mf = 3), with a c iss = 2058 pf (max) and r ds(mf) = 15m (max at t j = 125oc) and a fairchild fdd6682 as the synchronous mosfet (six total; n sf = 6), with c iss = 2880pf (max) and r ds(sf) = 11.9m (max at t j = 125oc). the synchronous mosfet c iss is less than 3000 pf, satisfying that requirement. solving for the power dissipation per mosfet at i o = 65a and i r = 8.86a yields 1.24w for each synchronous mosfet and 1.62w for each main mosfet. these numbers work well considering there is usually more pcb area available for each main mosfet versus each synchronous mosfet. one last item to look at is the power dissipation in the driver for each phase. this is best described in terms of the q g for the mosfets and is given by the following, where q gmf is the total gate charge for each main mosfet and q gsf is the total gate charge for each synchronous mosfet: also shown is the standby dissipation factor (i cc times the v cc ) for the driver. for the fan5009, the maximum dissipa- tion should be less than 400 mw. for our example, with i cc = 7 ma, q gmf = 24nc (max) and q gsf = 31nc (max), we find 202 mw in each driver, which is below the 400 mw dissipation limit. see the fan5009 data sheet for more details. ramp resistor selection the ramp resistor (r r ) is used for setting the size of the internal pwm ramp. this resistor?s value is chosen to pro- vide the best combination of thermal balance, stability, and transient response. the followi ng expression is used for determining the optimum value: where a r is the internal ramp amplifier gain, a d is the current balancing amplifier gain, r ds is the total low-side mosfet on-resistance, and c r is the internal ramp capacitor value. a close standa rd 1% resistor value is 301k . the internal ramp voltage magnitude can be calculated using: the size of the internal ramp can be made larger or smaller. if it is made larger, stability and transient response will improve, but thermal balance wi ll degrade. likewise, if the ramp is made smaller, thermal balance will improve at the sacrifice of transient response and stability. the factor of three in the denominator of equation 19 sets a ramp size that gives an optimal balance fo r good stability, transient response, and thermal balance. comp pin ramp there is a ramp signal on the comp pin due to the droop voltage and output voltage ramps. this ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the pwm input. for this example, the overall ramp signal is found to be 0.974v. current limit set point to select the current limit se t point, we need to find the resistor value for r lim . the current limit threshold for the fan5019b is set with a 3v source (v lim ) across r lim with a gain of 10.4mv/ma (a lim ). r lim can be found using the following: for r lim values greater than 500k , the current limit may be lower than expected, so some adjustment of r lim may be needed. here, i lim is the average curren t limit for the output of the supply. for our example, choosing 120a for i lim , we find r lim to be 200k , for which we chose 200k as the nearest 1% value. the per phase current limit described earlier has its limit determined by the following: for the fan5019b, the maximum comp voltage (v comp(max) ) is 3.3 v, the comp pin bias voltage (v bias ) is 1.2v, and the current balancing amplifier gain (a d ) is 5. using v r of 0.765v, and r ds(max) of 5.95m (low-side on-resistance at 125c), we find a per-phase limit of 40.44a. () cc cc gsf sf gmf mf sw drv v i q n q n n f p ? ? ? ? ? ? + + = 2 (18) r ds d r r c r a l a r = 3 (19) = = k pf m nh r r 291 5 95 . 5 5 3 650 2 . 0 () sw r r vid r r f c r v d a v ? = 1 (20) () v khz pf k v v r 765 . 0 228 5 301 5 . 1 125 . 0 1 2 . 0 = ? = ( ) ? ? ? ? ? ? ? ? ? ? = o x sw r rt r c f n d n v v 1 2 1 (21) o lim lim lim lim r i v a r = (22) 2 ) ( ) ( r max ds d bias r max comp phlim i r a v v v i ? ? ? ? (23)
fan5019b product specification 24 rev. 1.0.0 jul/15/05 () vid o x rt vid rt l ds d o e v r c n v d n l v v r r a r n r ? + + + = 1 2 (25) ( ) x o o x o x a r r r r l r r c t ' ' ? + ? = (26) ( ) s m m m m ph m m mf t a 79 . 4 0 . 1 6 . 0 3 . 1 3 . 1 375 6 . 0 3 . 1 56 . 6 = ? + ? = () x o x b c r r r t ? + = ' (27) () = ? + + + = m v m mf v nh v v m m m r e 3 . 55 5 . 1 3 . 1 56 . 6 3 974 . 0 375 . 0 1 650 2 5 . 1 974 . 0 6 . 1 95 . 5 5 3 . 1 3 this limit can be adjusted by changing the ramp voltage v r . do not set the per-phase limi t lower than the average per- phase current (i lim/n ). there is also a per phase initial duty cycle limit determined by: for this example, the maximum duty cycle is found to be 0.2696. feedback loop compensation design optimized compensation of the fan5019b allows the best possible response of the regulator?s output to a load change. the basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (r o ). with the resistive output impedance, the output voltage will droop in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output decoupling. with the multimode feedback structure of the fan5019b, the feedback compensation shou ld be set to make the con- verter?s output impedance work in conjunction with the out- put decoupling to meet this goal. the output inductor and decoupling capacitors (output fi lter) create several poles and zeros that require compensation. a type-iii compensator on the vo ltage feedback is adequate for proper compensati on of the output filter. the expressions given in equations 25?29 are intended to yield an optimal starting point for the design; some adjustments may be nec- essary to account for pcb and component parasitic effects (see the tuning procedure for the fan5019b section). the first step is to compute th e time constants for all of the poles and zeros in the system: where, for the fan5019b, r' is the pcb resistance from the bulk capacitors to the ceramics and where r ds is approxi- mately the total low-side mosfet on resistance per phase at 25oc. for this example, a d is 5, v rt equals 0.974v, r' is approximately 0.6m (assuming a 4-layer motherboard) and l x is 375ph for the eight al-poly capacitors. the compensation values can then be solved using the fol- lowing equations: rt bias max comp max v v v d d ? = ) ( (24) () s mf m m m t b 97 . 1 56 . 6 3 . 1 6 . 0 0 . 1 = ? + = e vid sw ds d rt c r v f r a l v t ? ? ? ? ? ? ? ? ? = 2 (28) s m v khz m nh v t c 86 . 6 3 . 55 5 . 1 228 2 95 . 6 5 650 974 . 0 = ? ? ? ? ? ? ? = ( ) o z o x o z x d r c r r c r c c t + ? = ' 2 (29) () ( ) ns m f m m mf m f mf t d 500 3 . 1 220 6 . 0 3 . 1 56 . 6 3 . 1 220 56 . 6 2 = + ? = b e a o a r r t r n c = (30) pf k m s m c a 253 33 . 1 3 . 55 79 . 4 3 . 1 3 = = = = = k pf s c t r a c a 1 . 27 253 86 . 6 () nf k s r t c b b b 48 . 1 33 . 1 97 . 1 = = = (32) pf k ns r t c a d fb 5 . 18 1 . 27 500 = = = (33)
product specification fan5019b rev. 1.0.0 jul/15/05 25 choosing the closest standard values for these components yields: c a = 390pf, r a = 16.9k , c b = 1.5nf, and c fb = 33pf. c in selection and input current di/dt reduction in continuous inductor-current mode, the source current of the high-side mosfet is approximately a square wave with a duty ratio equal to n (v out /v in ) and an amplitude of one- nth of the maximum output current. to prevent large voltage transients, use a low esr inpu t capacitor sized for the maxi- mum rms current. the maximu m rms capacitor current is given by: figure 6. typical transient r esponse for design example note that the capacitor manufact urer?s ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temp erature than required. several capacitors may be placed in parallel to meet size or height requirements in the design. in this example, the input capacitor bank is formed by three 2200f, 16v nichicon capacitors with a ripple cu rrent rating of 3.5a each. to reduce the input-current di/dt to below the recommended maximum of 0.1a/s, insert an additional small inductor (l > 1h @ 15a) between the converter and the supply bus. that inductor also acts as a f ilter between the converter and the primary power source. tuning procedure fo r the fan5019b dc load line setting 1. build a circuit based on compensation values computed from the design spreadsheet. 2. hook up dc load to circuit, turn on and verify opera- tion. also check for jitter at no-load and full-load. 3. measure output voltage at no-load (v nl ). verify it is within tolerance. figure 7. effi ciency vs. output current (circuit of figure 5) 4. measure output voltage at full-load cold (v flcold ). let board soak for ~10 minutes at full-load and measure output (v flhot ). if there is a change of more than a couple of millivolts, adjust r cs1 and r cs2 using equations 35 and 37. 5. repeat step 4 until cold and hot voltage measurements remain the same. 6. measure output voltage from no-load to full-load using 5 amp steps. compute th e loadline slope for each change and then average to get overall loadline slope (r omeas ). 7. if r omeas is off from r o by more than 0.05 m , use the following to adjust the r ph values: 8. repeat steps 6 and 7 to check loadline and repeat adjustments if necessary. 9. once the dc loadline adjustment is completed, do not change r ph , r cs1 , r cs2 , or r th for the rest of proce- dure. 1 1 ? = d n i d i o crms (34) a a i crms 5 . 10 1 125 . 0 3 1 65 125 . 0 = ? = () ( ) flhot nl flcold nl old cs new cs v v v v r r ? ? = ) ( 2 ) ( 2 (35) 80 100 60 40 20 0 20 0 40 output current (a) efficiency (%) 60 10 30 50 o omeas old ph new ph r r r r = ) ( ) ( (36)
fan5019b product specification 26 rev. 1.0.0 jul/15/05 (37) () ( ) ) 25 ( ) 25 ( ) ( 1 ) ( 2 ) ( 2 ) 25 ( ) ( 1 ) 25 ( ) ( ) ( 1 1 c th c th old cs new cs old cs c th old cs c th old cs new cs o o o o r r r r r r r r r r ? ? ? + + = 10. measure the output ripple at no-load and full-load with a scope and make sure it is within spec. ac loadline setting 11. remove dc load from circuit and hook up dynamic load. 12. hook up scope to output voltage and set to dc coupling with a time scale at 100s/div. 13. set dynamic load for a tran sient step of approximately 40a at 1khz with 50% duty cycle. 14. measure the output waveform (may have to use dc off- set on scope to see waveform). try to use a vertical scale of 100 mv/div or finer. 15. you will see a waveform that looks something like figure 8. use the horizontal cursors to measure v acdrp and v dcdrp as shown. note: do not measure the undershoot or overshoot that happens immediately after the step. figure 8. ac loadline waveform 16. if the v acdrp and v dcdrp are different by more than a couple of millivolts, use equation 38 to adjust c cs . you may need to parallel differen t values to get the right one since there are limited stan dard capacitor values avail- able (it is a good idea to ha ve locations for two capaci- tors in the layout for this). 17. repeat steps 11 to 13 and repeat adjustments if necessary. once complete, do not change c cs for the rest of the procedure. 18. set the dynamic load step to the maximum step size (do not use a step size larger than needed) and verify that the output waveform is square (which means vacdrp and vdcdrp are equal). note: make sure load step slew rate and turn-on are set for a slew rate of ~150?250a/s (for example, a load step of 50a should take 200ns?300ns) with no overshoot. some dynamic loads will have an excessive turn-on overshoot if a minimum current is not set properly (this is an issue if using a vtt tool). initial transient setting 19. with dynamic load still set at maximum step size, expand the scope time scale to see 2s/div to 5s/div. you will see a waveform that may have two overshoots and one minor undershoot (see figure 9). here, v droop is the final desired value. figure 9. transient setting waveform 20. if both overshoots are larger than desired, try making the following adjustments in this order. ( note : if these adjustments do not change th e response, you are limited by the output decoupling.) check the output response each time you make a change as well as the switching nodes (to make sure it is still stable). a. make ramp resistor larger by 25% (r ramp ). b. for v tran1 , increase cb or in crease switching fre- quency. c. for v tran2 , increase r a and decrease c a by 25%. 21. for load release (see figure 10), if v tranrel is larger than v tran1 (see figure 9), you do not have enough output capacitance. you will either need more capaci- tance or need to make the inductor values smaller (if you change inductors, you need to start the design over using the spreadsheet and this tuning procedure). 80 100 60 40 20 0 20 0 40 output current (a) efficiency (%) 60 10 30 50 dcdrp acdrp old cs new cs v v c c = ) ( ) ( (38)
product specification fan5019b rev. 1.0.0 jul/15/05 27 figure 10. transient setting waveform since the fan5019b turns off all of the phases (switches inductors to ground), there is no ripple voltage present during load release. thus, you do not have to add headroom for ripple, allowing your load release v tranrel to be larger than v tran1 by that amount and still be meeting spec. if v tran1 and v tranrel are less than the desired final droop, this implies that capacitors can be removed. when removing capacitors, check the output ripple voltage as well to ensure it is still within spec. layout and component placement the following guidelines are recommended for optimal performance of a switching regulator in a pc system. key layout issues are illustrated in figure 11. figure 11. layout recommendations general recommendations ? for good results, at least a four-layer pcb is recommended. this should allow the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input, and output power, and wide interconnectio n traces in the rest of the power delivery curr ent paths. keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. ? whenever high currents must be routed between pcb layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current pa ths is minimized and the via current rating is not exceeded. ? if critical signal lines (including the output voltage sense lines of the fan5019b) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry to serves as a shield to minimize noise injection into the signals.. ? use an analog ground plane both around and under the fan5019b for ground connections to the components associated with the controller. tie this plane to the nearest output decoupling capacitor ground and not to any other power circuitry to prevent power currents from flowing in it. ? connect the components around the fan5019b close to the controller with short tr aces. the most important traces to keep short and away from other traces are the fb and cssum pins. ? connect the output capacitors as close as possible to the load (or connector) that r eceives the power (e.g., a microprocessor core). if th e load is di stributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. power circuitry ? route the switching power path on the pcb to encompass the shortest possible length in order to minimize radiated switching noise energy (i.e., emi) and conduction losses in the board. failure to take proper precautions often results in emi problems for the entire pc system as well as noise related operational problems in the power converter control circuitry. the switching power path is the loop formed by the current path through the input capacitors and the power mosfets including all interconnecting pcb traces an d planes. the use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high-energy ringing, and it accommodates the hi gh current demand with minimal voltage loss. avoid crossing any signal lines over the switching power path loop, described below.
fan5019b product specification 28 rev. 1.0.0 jul/15/05 ? whenever a power dissipating component (e.g., a power mosfet) is soldered to a pcb, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. two important reasons for this are: improved curren t rating through the vias, and improved thermal performance from vias extended to the opposite side of the pcb wher e a plane can more readily transfer the heat to the air. to achieve the best thermal dissipation to the air around the board, make a mirror image of any pad being used to heatsink the mosfets on the opposite side of the pcb . to further improve thermal performance, use the largest possible pad area. ? route the output power path to encompass a short distance. the output power path is formed by the current path through the inductor, th e output capacitors, and the load. ? for best emi containment, use a solid power ground plane as one of the inner layers extending fully under all the power components. signal circuitry ? the output voltage is sensed and regulated between the fb pin and the fbrtn pin (which connects to the signal ground at the load). to avoid differential mode noise pickup in the sensed signal, the loop area should be small. thus the fb and fbrtn traces should be routed adjacent to each other atop the power ground plane back to the controller. ? connect the feedback traces from the switch nodes as close as possible to the inductor. connect the csref signal to the output voltage at the nearest inductor to the controller.
product specification fan5019b rev. 1.0.0 jul/15/05 29 mechanical dimensions 28-pin tssop 9 .7 0.1 15 ? b ? 0.1 c pin # 1 ident 14 all lead tips 0.2 land pattern recommendation 0.65 0.42 ba ? a ? 4.4 0.1 1.78 4.16 7.72 0.51 typ 28 3.2 6.4 1.2 max all lead tips 0.65 0.1 9 ?0.30 0.13 0. 9 0 see detail a 0.0 9 ?0.20 0.10 0.05 0 ?8 r0.31 r0.16 .025 gage plane seating plane detail a 0.61 0.1 dimensions are in millimeters notes: a. conforms to jedec registration mo-153, variation ab, ref. note 6, dated 7/ 9 3. b. dimensions are in millimeters. c. dimensions are exclusive of burrs, mold flash, and tie bar extensions. d dimensions and tolerances per ansi y14.5m, 1 9 82 1.00 12.00 top & botom +0.15 ?0.10 bc a ? c ?
fan5019b product specification jul/15/05 0.0m 005 stock#ds30005019 ? 2003 fairchild semiconductor corporation life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain lif e, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in an y component of a life support device or system whose fa ilure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com disclaimer fairchild semiconductor reserv es the right to make changes without further notice to any products herein to improve reliability, function or design. fa irchild does not assume any liability arising out of the application or use of any pr oduct or circuit described herein; neither does it convey any license under it s patent rights, nor the rights of others. ordering information part number temperature range pb free package packing FAN5019BMTCX 0c to +85c yes tssop-28 tape and reel

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